document number: 91056 www.vishay.com s-83029-rev. a, 19-jan-09 1 power mosfet IRF744, sihf744 vishay siliconix features ? dynamic dv/dt rating ? repetitive avalanche rated ? fast switching ? ease of paralleling ? simple drive requirements ? lead (pb)-free available description third generation power mosfets from vishay provides the designer with the best combi nation of fast switching, ruggedized device design, low on-resistance and cost effectiveness. the to-220 package is universally preferred for all commercial-industrial applications at power dissipation levels to approximately 50 w. the low thermal resistance and low package cost of the to-220 contribute to its wide acceptance throughout the industry. notes a. repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. v dd = 50 v, starting t j = 25 c, l = 12 mh, r g = 25 i as = 8.8 a (see fig. 12). c. i sd 8.8 a, dv/dt 200 a/s, v dd v ds , t j 150 c. d. 1.6 mm from case. product summary v ds (v) 450 r ds(on) ( )v gs = 10 v 0.63 q g (max.) (nc) 80 q gs (nc) 12 q gd (nc) 41 configuration single n-channel mosfet g d s to-220 g d s a v aila b le rohs* compliant ordering information package to-220 lead (pb)-free IRF744pbf sihf744-e3 snpb IRF744 sihf744 absolute maximum ratings t c = 25 c, unless otherwise noted parameter symbol limit unit drain-source voltage v ds 450 v gate-source voltage v gs 20 continuous drain current v gs at 10 v t c = 25 c i d 8.8 a t c = 100 c 5.6 pulsed drain current a i dm 35 linear derating factor 1.0 w/c single pulse avalanche energy b e as 540 mj repetitive avalanche current a i ar 8.8 a repetitive avalanche energy a e ar 13 mj maximum power dissipation t c = 25 c p d 125 w peak diode recovery dv/dt c dv/dt 3.5 v/ns operating junction and storage temperature range t j , t stg - 55 to + 150 c soldering recommendations (p eak temperature) for 10 s 300 d mounting torque 6-32 or m3 screw 10 lbf in 1.1 n m * pb containing terminations are not rohs compliant, exemptions may apply
www.vishay.com document number: 91056 2 s-83029-rev. a, 19-jan-09 IRF744, sihf744 vishay siliconix notes a. repetitive rating; pulse width limited by maximum junction temper ature (see fig. 11). b. pulse width 300 s; duty cycle 2 %. thermal resistance ratings parameter symbol typ. max. unit maximum junction-to-ambient r thja -62 c/w case-to-sink, flat, greased surface r thcs 0.50 - maximum junction-to-case (drain) r thjc -1.0 specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 450 - - v v ds temperature coefficient v ds /t j reference to 25 c, i d = 1 ma - 0.59 - v/c gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 2.0 - 4.0 v gate-source leakage i gss v gs = 20 - - 100 na zero gate voltage drain current i dss v ds = 450 v, v gs = 0 v - - 25 a v ds = 360 v, v gs = 0 v, t j = 125 c - - 250 drain-source on-state resistance r ds(on) v gs = 10 v i d = 5.3 a b --0.63 forward transconductance g fs v ds = 50 v, i d = 5.3 a b 4.5 - - s dynamic input capacitance c iss v gs = 0 v v ds = 25 v f = 1.0 mhz, see fig. 5 - 1400 - pf output capacitance c oss - 370 - reverse transfer capacitance c rss - 140 - total gate charge q g v gs = 10 v i d = 8.8 a, v ds = 360 v, see fig. 6 and 13 b --80 nc gate-source charge q gs --12 gate-drain charge q gd --41 turn-on delay time t d(on) v dd = 225 v, i d = 8.8 a r g = 9.1 , r d = 25 , see fig. 10 b -8.7- ns rise time t r -28- turn-off delay time t d(off) -58- fall time t f -27- internal drain inductance l d between lead, 6 mm (0.25") from package and center of die contact -4.5- nh internal source inductance l s -7.5- drain-source body diode characteristics continuous source-drain diode current i s mosfet symbol showing the integral reverse p - n junction diode --8.8 a pulsed diode forward current a i sm --35 body diode voltage v sd t j = 25 c, i s = 8.8 a, v gs = 0 v b -- 2.0 v body diode reverse recovery time t rr t j = 25 c, i f = 8.8 a, di/dt = 100 a/s b - 490 740 ns body diode reverse recovery charge q rr - 3.2 4.8 c forward turn-on time t on intrinsic turn-on time is neglig ible (turn-on is dominated by l s and l d ) d s g s d g
document number: 91056 www.vishay.com s-83029-rev. a, 19-jan-09 3 IRF744, sihf744 vishay siliconix typical characteristics 25 c, unless otherwise noted fig. 1 - typical output characteristics, t c = 25 c fig. 2 - typical output characteristics, t c = 150 c fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature 91056_01 bottom to p v gs 15 v 10 v 8 .0 v 7.0 v 6.0 v 5.5 v 5.0 v 4.5 v 20 s p u lse w idth t c = 25 c 4.5 v v ds , drain-to-so u rce v oltage ( v ) i d , drain c u rrent (a) 10 0 10 1 10 1 10 0 10 1 10 0 10 0 10 1 v ds , drain-to-so u rce v oltage ( v ) i d , drain c u rrent (a) bottom to p v gs 15 v 10 v 8 .0 v 7.0 v 6.0 v 5.5 v 5.0 v 4.5 v 20 s p u lse w idth t c = 150 c 91056_02 4.5 v 20 s p u lse w idth v ds = 50 v 10 1 10 0 i d , drain c u rrent (a) v gs , gate-to-so u rce v oltage ( v ) 567 8 910 4 25 c 150 c 91056_03 i d = 8 . 8 a v gs = 10 v 3.0 0.0 0.5 1.0 1.5 2.0 2.5 t j , j u nction temperat u re ( c) r ds(on) , drain-to-so u rce on resistance ( n ormalized) 91056_04 - 60 - 40 - 20 0 20 40 60 8 0 100 120 140 160 3.5
www.vishay.com document number: 91056 4 s-83029-rev. a, 19-jan-09 IRF744, sihf744 vishay siliconix fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical gate charge vs. gate-to-source voltage fig. 7 - typical source-drain diode forward voltage fig. 8 - maximum safe operating area 3000 2500 2000 1500 0 500 1000 10 0 10 1 capacitance (pf) v ds , drain-to-so u rce v oltage ( v ) c iss c rss c oss v gs = 0 v , f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gd 91056_05 q g , total gate charge (nc) v gs , gate-to-so u rce v oltage ( v ) 20 16 12 8 0 4 020 8 0 60 40 v ds = 90 v v ds = 225 v for test circ u it see fig u re 13 v ds = 360 v 91056_06 i d = 8 . 8 a 10 1 10 0 v sd , so u rce-to-drain v oltage ( v ) i sd , re v erse drain c u rrent (a) 0.4 1.2 1.0 0. 8 0.6 25 c 150 c v gs = 0 v 91056_07 10 -1 1.6 1.4 10 s 100 s 1 ms 10 ms operation in this area limited b y r ds(on) v ds , drain-to-so u rce v oltage ( v ) i d , drain c u rrent (a) t c = 25 c t j = 150 c single p u lse 10 2 2 5 0.1 2 5 1 2 5 10 2 5 25 110 25 10 2 10 3 25 91056_0 8 10 3
document number: 91056 www.vishay.com s-83029-rev. a, 19-jan-09 5 IRF744, sihf744 vishay siliconix fig. 9 - maximum drain current vs. case temperature fig. 10a - switching time test circuit fig. 10b - switching time waveforms fig. 11 - maximum effective transient thermal impedance, junction-to-case fig. 12a - unclamped inductive test circui t fig. 12b - unclamped inductive waveforms i d , drain c u rrent (a) t c , case temperat u re (c) 0 2 4 6 8 10 25 150 125 100 75 50 91056_09 p u lse w idth 1 s d u ty factor 0.1 % r d v gs r g d.u.t. 10 v + - v ds v dd v ds 90 % 10 % v gs t d(on) t r t d(off) t f 10 1 0.1 10 -2 10 -5 10 -4 10 -3 10 -2 0.1 1 10 p dm t 1 t 2 t 1 , rectang u lar p u lse d u ration (s) thermal response (z thjc ) n otes: 1. d u ty factor, d = t 1 /t 2 2. peak t j = p dm x z thjc + t c single p u lse (thermal response) d = 0.5 0.2 0.05 0.02 0.01 91056_11 0.1 r g i as 0.01 t p d.u.t l v ds + - v dd 10 v v ary t p to o b tain re qu ired i as i as v ds v dd v ds t p
www.vishay.com document number: 91056 6 s-83029-rev. a, 19-jan-09 IRF744, sihf744 vishay siliconix fig. 12c - maximum avalanche energy vs. drain current fig. 13a - basic gate charge waveform fig. 13b - gate charge test circuit 1200 0 200 400 600 8 00 1000 25 150 125 100 75 50 starting t j , j u nction temperat u re (c) e as , single p u lse energy (mj) bottom to p i d 3.9 a 5.6 a 8 . 8 a v dd = 50 v 91056_12c q gs q gd q g v g charge 10 v d.u.t. 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v current regulator current sampling resistors same type as d.u.t. + -
document number: 91056 www.vishay.com s-83029-rev. a, 19-jan-09 7 IRF744, sihf744 vishay siliconix fig. 14 - for n-channel vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91056 . p.w. period di/dt diode recovery dv/dt ripple 5 % body diode forward drop re-applied voltage reverse recovery current body diode forward current v gs = 10 v* v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor current d = p. w . period + - + + + - - - * v gs = 5 v for logic level devices peak diode recovery dv/dt test circuit r g v dd ? dv/dt controlled by r g ? driver same type as d.u.t. ? i sd controlled by duty factor "d" ? d.u.t. - device under test d.u.t circuit layout considerations ? low stray inductance ? ground plane ? low leakage inductance current transformer
document number: 91000 www.vishay.com revision: 18-jul-08 1 disclaimer legal disclaimer notice vishay all product specifications and data are subject to change without notice. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, ?vishay?), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. vishay disclaims any and all li ability arising out of the use or application of any product describ ed herein or of any information provided herein to the maximum extent permit ted by law. the product specifications do not expand or otherwise modify vishay?s terms and conditions of purcha se, including but not limited to the warranty expressed therein, which apply to these products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of vishay. the products shown herein are not designed for use in medi cal, life-saving, or life-sustaining applications unless otherwise expressly indicated. customers using or selling vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify vishay for any damages arising or resulting from such use or sale. please contact authorized vishay personnel to obtain written terms and conditions regarding products designed for such applications. product names and markings noted herein may be trademarks of their respective owners.
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